module led_state(
	input clk_1Hz,
	input rst_n,
	output reg flag,
	output reg[13:0] led_state
);
	
	reg left_flag;
	reg right_flag;

	always @(posedge clk_1Hz or negedge rst_n) begin
		if(rst_n == 1'b0) begin
			led_state = 14'b000_0000_0001_111;
			flag = 1'b0;
			left_flag = 1'b1;
			right_flag = 1'b0;
		end
		else begin
			if(led_state == 14'b111_1000_0000_000) begin
				flag = 1'b1;
				if(right_flag == 1'b0) begin
					right_flag = 1'b1;
				end
				else begin
					right_flag = 1'b0;
					led_state = led_state >> 1;
				end
			end
			else if(led_state == 14'b000_0000_0001_111) begin
				flag = 1'b0;
				if(left_flag == 1'b0) begin
					left_flag = 1'b1;
				end
				else begin
					left_flag = 1'b0;
					led_state = led_state << 1;
				end
			end
			else begin
				if(flag == 1'b0) begin
					led_state = led_state << 1;
				end
				else begin
					led_state = led_state >> 1;
				end
			end
		end
	end

endmodule
